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features ? number of keys: ?up to 4 ? discrete outputs: ? 4 discrete outputs indicati ng individual key touch ? technology: ? patented spread-spectrum charge-transfer (direct mode) ? electrode design: ? simple self-capacitance style (refer to the touch sensors design guide ) ? electrode materials: ? etched copper, silver, carbon, indium tin oxide (ito) ? electrode substrates: ? pcb, fpcb, plastic films, glass ? panel materials: ? plastic, glass, composites, painted surfa ces (low particle dens ity metallic paints possible) ? panel thickness: ? up to 10 mm glass, 5 mm plastic (electrode size dependent) ? key sensitivity: ? fixed key threshold, sensitivity ad justed via sample capacitor value ? adjacent key suppression ? ? patented adjacent key suppression ? (aks ? ) technology to enable accurate key detection ? interface: ? pin-per-key outputs, plus debu g mode to obser ve sensor signals ? moisture tolerance: ?good ? power: ? 1.8v ~ 5.5v ? package: ? 20-pin 3 x 3 mm vqfn rohs compliant ? signal processing: ? self-calibration, auto drift compensation, noise filtering, adjacent key suppression technology ? applications: ? mobile, consumer, white goods, toys, kiosks, pos, and so on qtouch ? 4-key sensor ic AT42QT1040 9524a?at42?03/09
2 9524a?at42?03/09 AT42QT1040 1. pinout and schematic 1.1 pinout configuration i/o cmos input and output od cmos open drain output p ground or power table 1-1. pin listing pin name type function notes if unused... 1 sns2 i/o sense pin to cs2 leave open 2 snsk1 i/o sense pin to cs1 + key leave open 3sns1i/o sense pin and option detect to cs1 and/or option resistor connect to option resistor* 4 snsk0 i/o sense pin to cs0 + key leave open 5sns0i/o sense pin and option detect to cs0 and/or option resistor connect to option resistor* 6n/c? ? ? 7n/c? ? ? 8 vss p supply ground ? 9 vdd p power ? 10 n/c ? ? ? 11 out0 od out 0 alternative function: debug clk leave open 12 out1 od out 1 alternative function: debug data leave open 13 out3 od out 3 leave open 14 out2 od out 2 leave open 15 snsk3 i/o sense pin to cs3 + key leave open 16 sns3 i/o sense pin to cs3 leave open 17 n/c ? ? ? 18 n/c ? ? ? 19 n/c ? ? ? 20 snsk2 i/o sense pin to cs2 + key leave open * option resistor should always be fitted even if ch annel is unused and cs capacitor is not fixed. n/c n/c vss vdd n/c sns2 snsk1 sns1 snsk0 sns0 out0 out1 1 2 3 4 5 11 12 13 14 15 20 19 18 17 16 6 7 8 10 9 qt1040 out3 out2 snsk3 sns3 n/c snsk2 n/c n/c
3 9524a?at42?03/09 AT42QT1040 1.2 schematic figure 1-1. typical circuit suggested regulator manufacturers: ? torex (xc6215 series) ? seiko (s817 series) ? bcdsemi (ap2121 series) re figure 1-1 check the following sectio ns for component values: ? section3.1 on page6 : cs capacitors (cs0 ? cs3) ? section3.5 on page7 : voltage levels ? section3.3 on page6 : led traces slow fast off led3 led2 led0 led1 vdd vdd 2 1 3 j2 vdd 2 1 3 j1 on 2 2 5 5 4 4 3 3 1 1 j3 vdd 9 vss 8 n/c 19 n/c 10 out2 14 snsk3 15 snsk2 20 snsk1 2 snsk0 4 n/c 18 n/c 7 n/c 17 out1 12 out0 11 sns3 16 sns1 3 n/c 6 out3 13 sns0 5 sns2 1 speed select aks select notes: 1) the central pad on the underside of the vqfn chip is a vss pin and should be connected to ground. do not put any other tracks underneath the body of the chip. 2) it is important to place all cs and rs components physically near to the chip. add a 100 nf capacitor close to pin 9. qt1040 creg creg vreg follow regulator manufacturer's recommended values for input and output bypass capacitors (creg). key0 key1 key2 key3 vunreg gnd cs0 cs1 cs2 cs3 rl0 rl1 rl2 rl3 raks rfs rs0 rs1 rs2 rs3 example use of output pins
4 9524a?at42?03/09 AT42QT1040 2. overview of the AT42QT1040 2.1 introduction the AT42QT1040 (qt1040) is a digital burst mode charge-transfer (qt ? ) capacitive sensor driver designed for touch-key applications. the device can sense from one to four keys; one to three keys can be disabled by not installing their respective sense capacitors. any of the four channels can be disabled in this way. the device includes all signal processing functions necessary to provide stable sensing under a wide variety of changing conditions, and the outputs are fully debounced. only a few external parts are required for operation. the qt1040 modulates its bursts in a spread-spectrum fashion in order to heavily suppress the effects of external noise, and to suppress rf emissions. 2.2 signal processing 2.2.1 detect threshold the internal signal threshold leve l is fixed at 10 counts of c hange with respect to the internal reference level. this in turn adjusts itself slowly in accordance with the drift compensation mechanism. see section 3.1 on page 6 for details on how to adju st each key?s sensitivity. when going out of detect there is a hysteresis element to the detection. the signal threshold must drop below 8 counts of change with respect to the internal reference level to register as un- touched. 2.2.2 detection integrator the device features a detection integration mec hanism, which acts to confirm a detection in a robust fashion. a per-key counter is incremented each time the key has exceeded its threshold, and a key is only finally declared to be touched when this counter reaches a fixed limit of 5. in other words, the device has to exceed its threshold, and stay there for 5 acquisitions in succession without going below the threshold level, before the key is declared to be touched. 2.2.3 burst length limitations burst length is the number of times the charge transfer process is performed on a given channel; that is, the number of pulses it takes to measure the key?s capacitance. the maximum burst length is 2048 pulses. the recommended design is to use a capacitor that gives a signal of <1000 pulses. longer bursts take more time and use more power. note that the keys are independent of each other. it is therefore possible, for example, to have a signal of 100 on one key and a signal of 1000 on another. refer to applicatio n note qtan0002, secrets of a successful qtouch? design (downloadable from the atmel ? website), for more information on using a scope to measure the pulses and hence determine the burst length. refer also to the touch sensors design guide . 2.2.4 adjacent key suppression technology the device includes atme l?s patented adjace nt key suppression (aks) technology, to allow the use of tightly spaced keys on a keypad wit h no loss of selectability by the user. there is one global aks group, implemented so that only one key in the group may be reported as being touched at any one time.
5 9524a?at42?03/09 AT42QT1040 the use of aks is selected by connecting a 1 m ? resisitor between vdd and the snsk0 pin (see section 4.1 on page 8 for more informati on). when aks is disabled, any combinations of keys can ente r detect. 2.2.5 auto drift compensation signal drift can occur because of c hanges in cx and cs over time. it is crucial that drift be compensated for, otherwise false detections, non-d etections, and sensitivity shifts will follow. drift compensation is performed by making the reference level track the raw signal at a slow rate, but only while there is no detection in effect. the rate of adjustment must be performed slowly otherwise legitimate detections could be ignored. once an object is sensed and a key is in detect, the drift compensation mechanism ceases, since the signal is legitimate ly high and should not therefore cause the reference level to change. the qt1040's drift compensation is ?asymmetric?: the reference level drift-compensates in one direction faster than it does in the other. spec ifically, it compensates faster for decreasing (towards touch) signals than for increasing (away from touch) signals. the reason for this difference in compensation rates is that increasing signals should not be compensated for quickly, since a nearby finger could be compen sated for partially or entirely before even approaching the sense electrode. however, decreasing signals need to be compensated for more quickly. for example, an obstruction over the sense pad (for which the sensor has already made full allowance) could suddenly be removed, leaving the sensor with an artificially elevated reference level and thus become insensitive to touch. in this latter case, the sensor will compensate for the object's removal very quickly, usually in only a few seconds. negative drift (that is, towards touch) occurs at a rate of ~3 seconds, while positive drift occurs at a rate of ~1 second. drifting only occurs when no keys are in detect state. 2.2.6 response time the qt1040's response time is highly dependent on run mode and burst length, which in turn is dependent on cs and cx. with increasing cs, response time slows, while increasing levels of cx reduce response time. th e response time will also be slower in slow mode due to a longer time between burst measurements. this mode offers an increased detection latency in favor of reduced average current consumption. 2.2.7 spread spectrum the qt1040 modulates its internal oscillator by 7.5 percent during the measurement burst. this spreads the generated noise over a wider band reducing emission levels. this also reduces susceptibility since there is no longer a single fundamenta l burst frequency. 2.2.8 max on-duration if an object or material obstructs the sense pad, the signal may rise enough to create a detection, preventing further operation. to prevent this, the sensor includes a timer known as the max on-duration feature which monitors detections. if a detection exceeds the timer setting, the sensor performs an automatic recalibration. max on-duration is set to ~30s.
6 9524a?at42?03/09 AT42QT1040 3. wiring and parts 3.1 cs sample capacitors cs0 ? cs3 are the charge sensing sample capacitors; normally they are identical in nominal value. the optimal cs values depend on the corresponding keys electrode design, the thickness of the panel and its dielectric constant. thicker panels require larger values of cs. values can be in the range 2.2 nf (for faster operation) to 22 nf (for best sensitivity); typical values are 4.7 nf to 10 nf. the value of cs should be chosen such that a light touch on a key mounted in a production unit or a prototype panel causes a reliable detectio n. the chosen cs value should never be so large that the key signals exceed ~1000, as reported by the chip in the debug data. the cs capacitors must be x7r or pps film type, for stab ility. for consistent sensitivity, they should have a 10 percent tolerance. twenty perc ent tolerance may cause small differences in sensitivity from key to key and unit to unit. if a key is not used, the cs capacitor may be omitted. 3.2 rs resistors the series resistors rs0 ? rs3 are inline with th e electrode connections (close to the qt1040 chip) and are used to limit electrostatic discharge (esd) currents and to suppress radio frequency (rf) interference. a typical value is 4.7 k ? , but up to 20 k ? can be used if it is found to be of benefit. although these resistors may be omitted, the device may become susceptib le to external noise or radio frequency interference (rfi). for details on how to select these resistors refer to application note qtan0002, secrets of a successful qtouch ? design , and the touch sensors design guide , both downloadable from the touch technology area of atmel?s website, www.atmel.com. 3.3 led traces and ot her switching signals for advice on leds and nearby traces, refer to application note qtan0002, secrets of a successful qtouch ? design , and the touch sensors design guide , both downloadable from the touch technology area of atmel?s website, www.atmel.com. 3.4 pcb cleanliness modern no-clean flux is generally compat ible with capacitive sensing circuits. if a pcb is reworked in any way, clean it thorou ghly to remove all traces of the flux residue around the capacitive sensor components. dry it thoroughly before any further testing is conducted. caution: if a pcb is reworked in any way, it is almost guaranteed that the behavior of the no-clean flux will change. this can me an that the flux ch anges from an inert material to one that can absorb moisture and dramatically affect capacitive measurements due to additional leakage currents. if so, the circuit can become erratic and exhi bit poor environmental stability.
7 9524a?at42?03/09 AT42QT1040 3.5 power supply see section5.2 on page13 for the power supply range. if the power supply fluctuates slowly with temperature, the device tracks and compens ates for these changes automatically with only minor changes in sensitivity. if the supply voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep up, causing sensitivity anomalies or false detections. the usual power supply considerations with qt parts apply to the device. the power should be clean and come from a separate regulator if possible. however, this device is designed to minimize the effects of unstable power, and exce pt in extreme conditi ons should not require a separate low dropout (ldo) regulator. see under figure 1.2 on page 3 for suggested regulator manufacturers. it is assumed that a larger bypass capacitor (for example, 1 f) is somewhere else in the power circuit; for example, near the regulator. to assist with transient regulato r stability problems, the qt1040 waits 500 s any time it wakes up from a sleep state (that is, in sleep mode) before acquiring, to allow vdd to fully stabilize. 3.6 vqfn package restrictions the central pad on the underside of the vqfn chip should be connected to ground. do not run any tracks underneath the body of the chip, only ground. figure 3-1 shows an example of good/bad tracking. figure 3-1. examples of good and bad tracking caution: a regulator ic shared with other logic can result in erratic operation and is not advised. a single ceramic 0.1 f bypass capacitor, with short traces, should be placed very close to the power pins of the ic. failure to do so can result in device oscillation, high current consumption, erratic operation, and so on. example of good tracking example of bad tracking
8 9524a?at42?03/09 AT42QT1040 4. detailed operations 4.1 adjacent key suppression the use of aks is selected by the connection of a 1 m ? resistor (raks resistor) between the snsk0 pin and either vdd (aks mode on) or vss (aks mode off). note: changing the raks option will affect the sensit ivity of the particular key. always check that the sensitivity is suitable after a change. retune cs0 if necessary. 4.2 discrete outputs there are four discrete outputs (channels 0 to 3), located on pins out0 to out3 . an output pin goes active when the corresponding key is touched. the outputs are open-drain type and are active-low. on the out2 pin there is a ~500 ns low pulse occuring approximately 20 ms after a power- up/reset (see figure 4-1 for an example oscilloscope trace of this pulse at two zoom levels). this pulse may need to be considered from the system design perspective. the discrete outputs have sufficient current sink ing capability to directly drive leds. try to limit the sink current to less than 5 ma per output and be cautious if connecting leds to a power supply other than vdd; if the led supply is higher than vdd it may cause erratic behavior of the qt1040 and ?back-power? the qt1040 through its i/o pins. table 4-1. raks resistor raks connected to... mode vdd aks on vss aks off the raks resistor should alwa ys be connected to either vdd or vss and should not be changed during operation of the device.
9 9524a?at42?03/09 AT42QT1040 figure 4-1. ~500 ns pulse on out2 pin 4.3 speed selection speed selection is determined by a 1 m ? resistor (rfs resistor) connected between snsk1 and either vdd (fast mode) or vss (slow mode). in fast mode, the device sleeps for 16 ms betwee n burst acquisitions. in slow mode, the device sleeps for 64 ms between acquisitions. hence, slow mode conserves more power but results in slightly less responsiveness. note: the rfs resistor should always be connected to either vdd or vss and not changed during operation of t he device. changing the rfs option will affect the sensitivity of the particular key. always check that the sensitivit y is suitable after a change. retune cs1 if necessary. pulse on out2 sns0k out2 sns0k out2 ~20 ms power-on/ reset table 4-2. rfs resistor rfs connected to... mode vdd fast mode vss slow mode
10 9524a?at42?03/09 AT42QT1040 4.4 calibration calibration is the process by which the sensor chip assesses the background capacitance on each channel. during calibration, a number of samples are taken in quick succession to get a baseline for the channel?s reference value. calibration takes place ~50 ms afte r power is applied to the device. calibration also occurs if the max on-duration is exceeded or a positive re-calibration occurs. 4.5 debug mode an added feature to this device is a debug option w hereby internal parameters from the ic can be clocked out and monitored externally. debug mode is entered by shorting the cs3 capac itor (snsk3 and sns3 pins) on power-up and removing the short within 5 seconds. note: if the short is not removed within 5 second s, debug mode is still entered, but with channel 3 unusable until a re-c alibration occurs. note that as channel 3 will show up as being in detect, a recalibration will occur after max on-duratio n (~30 seconds). debug clk pin (out0 ) and debug data pin (out1 ) float while debug data is not being output and are driven outputs once debug output starts (that is, not open drain). the serial data is clocked out at a rate of ~200 khz, msb first, as in table 4-3 . table 4-3. serial data output byte purpose notes 0 frame number framing index number 0-255 1chip version upper nibble: major revision lower nibble: minor revision 2 reference 0 low byte unsigned 16-bit integer 3 reference 0 high byte 4 reference 1 low byte unsigned 16-bit integer 5 reference 1 high byte 6 reference 2 low byte unsigned 16-bit integer 7 reference 2 high byte 8 reference 3 low byte unsigned 16-bit integer 9 reference 3 high byte 10 signal 0 low byte unsigned 16-bit integer 11 signal 0 high byte 12 signal 1 low byte unsigned 16-bit integer 13 signal 1 high byte 14 signal 2 low byte unsigned 16-bit integer 15 signal 2 high byte 16 signal 3 low byte unsigned 16-bit integer 17 signal 3 high byte
11 9524a?at42?03/09 AT42QT1040 bit 7: this bit is set during calibration bits 4 ? 6: contains the number of keys active bits 0 ? 3: show the touch status of the corresponding keys figure 4-2 to figure 4-5 show the usefulness of the debug data out feature. channels can be monitored and tweaked to the specific application with great accuracy. figure 4-2. byte clocked out (~5 s period) 18 delta 0 low byte signed 16-bit integer 19 delta 0 high byte 20 delta 1 low byte signed 16-bit integer 21 delta 1 high byte 22 delta 2 low byte signed 16-bit integer 23 delta 2 high byte 24 delta 3 low byte signed 16-bit integer 25 delta 3 high byte 26 flags various operational flags unsigned bytes 27 flags2 28 status byte unsigned byte. see table 4-4 29 frame number repeat of framing index number in byte 0 table 4-4. status byte (byte 28) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cal number of keys (2-4) key 3 key 2 key 1 key 0 table 4-3. serial data output (continued) byte purpose notes
12 9524a?at42?03/09 AT42QT1040 figure 4-3. byte following byte (~ 30 s period) figure 4-4. full debug send (30 bytes) figure 4-5. debug lines floating between debug data sends (30 bytes, ~2 ms to send)
13 9524a?at42?03/09 AT42QT1040 5. specifications 5.1 absolute maxi mum specifications 5.2 recommended o perating conditions 5.3 dc specifications vdd -0.5 to +6.0v max continuous pin current, any control or drive pin 10 ma voltage forced onto any pin -0.5v to (vdd + 0.5) volts caution: stresses beyond those listed under absolute maximum specifications may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. ex posure to absolute maximum specification conditions for extended periods may affect device reliability operating temperature -40c to +85c storage temperature -55c to +125c vdd 1.8v to 5.5v supply ripple + noise 20 mv maximum cx capacitance per key 2 to 20 pf vdd = 5.0v, cs = 4.7 nf, ta = recommended range, unless otherwise noted parameter description min typ max units notes vil low input logic level 0.5v ? 0.3v v vih high input logic level 0.6 vdd vdd vdd + 0.5v v vol low output voltage 0 ? 0.7 v 10 ma sink current voh high output voltage 0.8 vdd ? vdd v 10 ma source current iil input leakage current ? <0.05 1 a rrst internal rst pull-up resistor 20 ? 50 k ?
14 9524a?at42?03/09 AT42QT1040 5.4 timing specifications 5.5 power consumption parameter description min typ max units notes t bs burst duration ? 3.5 ? ms cx = 5 pf, cs = 18 nf fc burst center frequency ? 119 khz fm burst modulation, percentage -7.5 ? +7.5 % t pw burst pulse width ? 2 ? s vdd (v) aks mode (raks) speed (rfs) power consumption (a) 1.8 off slow 31 off fast 104 on slow 36 on fast 114 3.3 off slow 100 off fast 340 on slow 117 on fast 380 5.0 off slow 215 off fast 710 on slow 245 on fast 800
15 9524a?at42?03/09 AT42QT1040 5.6 mechanical dimensions title drawing no. gpc rev. packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com 20m2 zfc b 20m2, 20-pad, 3 x 3 x 0.85 mm body, lead pitch 0.45 mm, 1.55 x 1.55 mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (vqfn) 10/24/0 8 15 14 1 3 12 11 1 2 3 4 5 16 17 1 8 19 20 10 9 8 7 6 d2 e2 e b k l pin #1 ch a mfer (c 0. 3 ) d e s ide view a1 y pin 1 id bottom view top view a1 a c c0.1 8 ( 8 x) 0. 3 ref (4x) common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a 0.75 0. 8 0 0. 8 5 a1 0.00 0.02 0.05 b 0.17 0.22 0.27 c 0.152 d 2.90 3 .00 3 .10 d2 1.40 1.55 1.70 e 2.90 3 .00 3 .10 e2 1.40 1.55 1.70 e ? 0.45 ? l 0. 3 5 0.40 0.45 k 0.20 ? ? y 0.00 ? 0.0 8
16 9524a?at42?03/09 AT42QT1040 5.7 marking either of the following two markings may be used: program week code number 1-52 where: a = 1 b = 2 ... z = 26 then using the underscore a = 27...z = 52 140 r1 pin 1 id code revision: 1.0 released abbreviation of part number: at42qt 1 0 40 140 r1x pin 1 id code revision: r1 = 1.0 released abbreviation of part number: at42qt 1 0 40 traceability code (y = last digit of year; for example, 9 = 2009, 0 = 2010, etc zz = assembly trace code) assembly location code yzz
17 9524a?at42?03/09 AT42QT1040 5.8 part number 5.9 moisture sensiti vity level (msl) revision history part number description AT42QT1040-mmh 20-pin 3 x 3 mm vqfn rohs compliant msl rating peak body temperature specifications msl1 260 o c ipc/jedec j-std-020 revision no. history revision a ? march 2009 ? initial release for chip revision 1.0
9524a?at42?03/09 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 01-05 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 touch technology division 1 mitchell point ensign way hamble southampton hampshire so31 4rf united kingdom tel: (44) 23-8056-5600 fax: (44) 23-8045-3939 product contact web site www.atmel.com technical support touch@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with at mel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and conditions of sale located on atmel?s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limi tation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibilit y of such damages. atmel makes no representations or warranties with respect to th e accuracy or completeness of the contents of this document and reserves the right to make changes to specif ications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained herein. unless specific ally provided otherwise, atmel products are not suitable for, and shall not be used in, automo tive applications. atmel?s products are not intended, authorized, or warranted for use as componen ts in applications intended to support or sustain life. ? 2009 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, and others are registered trademarks, adjacent key suppression ? , aks ? , qt ? , qtouch ? , and others are trademarks of atmel corporation or its subsidiaries. other terms and product names may be registered trademarks or trademarks of others.

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